Actualités

Semiconductor Engineering1 j
Rethinking Chip Debug
The semiconductor industry has spent decades mastering the art of integrated circuit physical verification. But as system-on-chip (SoC) designs push the boundaries of complexity—with more transistors, ...
Semiconductor Engineering1 j
Patterned MW-NSFETs For Sustainable Scaling (POSTECH)
A new technical paper titled “Patterned Multi-Wall Nanosheet FETs for Sustainable Scaling: Zero Gate Extension With Minimal ...
Semiconductor Engineering1 j
Novel Assembly Approaches For 3D Device Stacks
The next big leap in semiconductor packaging will require a slew of new technologies, processes, and materials, but collectively they will enable orders of magnitude ...
Semiconductor Engineering4 j
Distributing Intelligence Inside Multi-Die Assemblies
Disaggregration requires traffic cops and in-chip monitors to function as expected over time. The shift from SoCs to ...
Semiconductor Engineering5 j
HW Security: Multi-Agent AI Assistant Leveraging LLMs To Automate Key Stages of SoC Security Verification (U. of Florida)
An Agentic Approach for SoC Security Verification using Large Language Models” was published by researchers at University of ...
Semiconductor Engineering3 j
Viability of aZnMIm As A Resist For EUV Lithography (Johns Hopkins, Northwestern, Intel et al.)
A new technical paper (preprint) titled “Extreme Ultraviolet and Beyond Extreme Ultraviolet Lithography using Amorphous ...
Semiconductor Engineering3 j
GNN-Based Framework for Hardware Trojan Detection, Including RISC-V Cores
Hardware Trojans Detection Using GNN in RTL Designs” was published by researchers at University of Connecticut and University ...
Semiconductor Engineering4 j
Redefining SoC Design: The Shift To Secure Chiplet-Based Architectures
Ensuring trusted execution across multiple chiplets and vendors is more complex than in traditional monolithic SoCs.
Semiconductor Engineering3 j
Chip Industry Week in Review
DAC's AI focus; 300mm fab report; foundry revenue; new auto chip org.; Micron earnings; rare earth exports plummet; UK's tech ...
Semiconductor Engineering6 j
Device Architecture For 2D Material-Based mNS-FETs In Sub-1nm Nodes (Sungkyunkwan Univ., Alsemy)
A new technical paper titled “Exploring optimal TMDC multi-channel GAA-FET architectures at sub-1nm nodes” was published by ...
Semiconductor Engineering7 j
EDA’s Top Execs Map Out An AI-Driven Future
AI requires a lot of data, particularly for training models. The problem is that planar chips are unable to process all that ...
Semiconductor Engineering12 j
Can You Build A Known-Good Multi-Die System?
Just because the various components in an advanced package work individually and together doesn't guarantee they will work ...