The next big leap in semiconductor packaging will require a slew of new technologies, processes, and materials, but collectively they will enable orders of magnitude ...

The semiconductor industry has spent decades mastering the art of integrated circuit physical verification. But as system-on-chip (SoC) designs push the boundaries of complexity—with more transistors, ...

A new technical paper titled “Patterned Multi-Wall Nanosheet FETs for Sustainable Scaling: Zero Gate Extension With Minimal ...

Hardware Trojans Detection Using GNN in RTL Designs” was published by researchers at University of Connecticut and University ...

A new technical paper (preprint) titled “Extreme Ultraviolet and Beyond Extreme Ultraviolet Lithography using Amorphous ...

DAC's AI focus; 300mm fab report; foundry revenue; new auto chip org.; Micron earnings; rare earth exports plummet; UK's tech ...

Disaggregration requires traffic cops and in-chip monitors to function as expected over time. The shift from SoCs to ...

Ensuring trusted execution across multiple chiplets and vendors is more complex than in traditional monolithic SoCs.

Analog and mixed signal content is adding risk to ASIC designs. Pessimists see the problem getting worse, while optimists point to AI and chiplets for relief.

For many aspects of an EDA flow, hallucinations from AI are not really that serious, because that is no worse than engineers on a Friday afternoon.

New tools and techniques are being developed and can help keep the verification process secure, alongside a firm foundation of good design verification practices.

An Agentic Approach for SoC Security Verification using Large Language Models” was published by researchers at University of ...