GitHub

A simple memory management simulator in C that supports paging including address translation, TLB implementation and page faults handling.

In this setup the logical address space (2^16 = 65,536 bytes) is larger than the physical address space (2^15 bytes), and the page size is 256 bytes. The maximum no. of entries in the TLB = 16.
IEEE

DTLB: Deterministic TLB for Tightly Bound Hard Real-Time Systems

Abstract: This paper proposes a novel TLB architecture - Deterministic Translation Lookaside Buffer - to reduce TLB misses, energy consumption and effective per access time. DTLB offers tighter upper ...
IEEE

TLB Coalescing for Multi-Grained Page Migration in Hybrid Memory Systems

Abstract: Superpages have long been proposed to enlarge the coverage of translation lookaside buffer (TLB). They are extremely beneficial for reducing address translation overhead in big memory ...
GitHub

100% TLB hit rate collected from gemmini counter

I tried to get the TLB miss rate when running MLP test and conv.c test using verilator. But all of these hit rate are 100%. What I did in test file is to add counter_configure(0, DMA_TLB_MISS_CYCLE); ...
TweakTown

AMD Phenom TLB patch benchmarked

Scott Wasson from The Tech Report is on the ball - he benchmarked an AMD Phenom processor affected by the translation lookaside buffer (TLB) and L3 cache bug which is said to be rare but could cause ...