IEEE

VHDL simulation of reset automatic block, 64 bit latch block, and test complete blocks for PD detection circuit system using FPGA

Abstract: This paper is purely a model to determine the design circuit to implement Partial Discharge (PD) detection in FPGA technology. The research shall involve ISE Simulator version 10.1i (Xilinx) ...
Hackaday

Xilinx Borrows Code For Their Own Devices

Back in 2012, [tmbinc] discovered a neat little undocumented feature in the Xilinx ISE: the ability to use TCP/IP instead of JTAG cables. [tmbinc] was working on an Open Hardware USB analyzer and ...
IEEE

VHDL implementation for measurement of the distance test distribution pattern of the Tri-Axial magnetic probe for the PD detection circuit system by using 3 GHz ADC and FPGA

Abstract: This paper is purely a model to implement Partial Discharge (PD) detection in FPGA technology and then implement the VHDL modeled in FPGA technology for measurement of the distance test ...