IEEE

Overview on Latch-Up Prevention in CMOS Integrated Circuits by Circuit Solutions

Abstract: In CMOS chips, the wider layout rules were traditionally applied to overcome latch-up issues. However, the chip area with wider layout rules was often enlarged, and in turn the chip cost was ...
IEEE

Shifting time waveform induced CMOS latch up in bootstrapping technique applications

Abstract: In this study, latch-up mechanisms of the complementary-metal-oxide-semiconductor (CMOS) in bootstrapping technique applied to DC/DC buck converter circuit has been clearly investigated by ...
Semiconductor Engineering

Robust Latch Hardened Against QNUs for Safety-Critical Applications in 22nm CMOS Technology

A technical paper titled “Cost-Optimized and Robust Latch Hardened against Quadruple Node Upsets for Nanoscale CMOS” was just published by researchers at Anhui University, Hefei University of ...
Techniques de l'Ingénieur

CMOS Integrated Circuits on Silicon

Advanced CMOS integrated circuits are now implemented in so-called thin-film technologies (FinFET, FDSOI), to improve the electrostatic control of the channel. These technologies are presented briefly ...