GitHub

This project implements an I²C counter on an FPGA. It demonstrates a professional hardware design workflow by integrating a custom Verilog module

Project Overview This project demonstrates a self-contained digital system that uses the I²C protocol to control a simple 8-bit counter. The system is built in Quartus Prime Lite v24.1 and verified ...
GitHub

ECE-745-ASIC-Verification

Repository containing a System Verilog testbench for verifying a I2C Multi-Bus Controller IP for interconversion between the Wishbone and I2C protocol. The testbench simulates a Wishbone Master and an ...
IEEE

Performance Analysis of Communication Protocols (I2C, SPI) for Embedded Applications with IMU Sensor using Verilog

Abstract: Effective communication protocols are to be ensured in crucial embedded application that helps for timely data transfer in connected environments, impacting efficiency, energy use, and ...
Design-Reuse

Digital Blocks Validates Existing I2C Slave Controller IP Core Family Compatibility with MIPI I3Cs

GLEN ROCK, New Jersey, Nov. 06, 2016 – Digital Blocks, a leading developer of silicon-proven semiconductor Intellectually Property (IP) soft cores for system-on-chip (SoC) ASIC, ASSP, & FPGA ...
Design-Reuse

Digital Blocks AMBA Peripherals I3C, I2C, eSPI, xSPI Controller IP Core Families Extend Leadership with enhancements containing feature-rich, system-level integration features.

GLEN ROCK, New Jersey, January 8, 2023 – Digital Blocks, a leading developer of silicon-proven semiconductor Intellectually Property (IP) soft cores for system-on-chip (SoC) ASIC, ASSP, & FPGA ...