IEEE

A low phase noise 10-G bits/s clock and data recovery circuit with modified D latch for backplane applications using dual loop architecture

Abstract: In this paper a clock and data recovery circuit (CDR) with modified D latch is designed meeting the standards of 10 Base-KR standard backplane. The designed circuit employs dual loop ...
IEEE

Monolithically integrated Si/SiGe resonant interband tunneling diodes/CMOS MOBILE latch with high voltage swing

Abstract: The Si/SiGe RITDs grown by MBE have been monolithically integrated with CMOS for the first time. The integrated devices resulted in a PVCR (peak-to-valley current ratio) of 2.8 at room ...