GitHub

sequential-circuits

This repository contains my assignments and projects for the Digital Systems course. The course covers the fundamental concepts of digital systems, including Boolean algebra, logic gates, ...
GitHub

This repository contains four laboratory assignments covering combinational circuits, sequential logic with Verilog, FPGA implementation, and memory systems.

Simplify and implement a circuit with inputs A1, A0, B1, B0 and outputs X, Y, Z using only 74LS ICs in Logisim. Learn Boolean algebra simplification and basic gate usage. Lab 2: Multiplexers, Decoders ...
IEEE

Combinational fault simulation in sequential circuits

Abstract: We propose a very fast fault simulation method which is based on exact parallel critical path tracing developed for combinational circuits. To convert the sequential problem of fault ...
Embedded

Configuring a PSoC for a DIY oscilliscope/logic analyzer – Part 2

Select between the Combination or Sequential circuit for analysis (Figure 16). Figure 16: Screen to select Combinational or Sequential Circuit Select the number of inputs (max of 3) and number of ...
电子工程专辑

combinational clock gating Vs sequential clock gating

关于clock gating 已经写过：《clock gating | 从ICG cell 在 library 中的定义说起》《clock gating | Gating 的插入与验证》《clock gating | clock gating 的timing check》《clock gating | ODC-based Clock Gating》。最近在学习 ...
EDN

A novel approach for simulation of digital circuits using levelization

Verification had always been an important part of SOC design flow. As SOCs are getting more and more complex, so is their verification. Verification of a design involves simulating the all possible ...