IEEE

Logical circuit gate sizing using PSO guided by Logical Effort — An examination of the 4-stage half adder circuit

Abstract: Automated Complementary Metal Oxide Semiconductor (CMOS) logic circuit design leads to the reduction in costs associated with manpower and manufacturing time. Conventional methods use ...
Nature

CMOS-based carbon nanotube pass-transistor logic integrated circuits

Field-effect transistors based on carbon nanotubes have been shown to be faster and less energy consuming than their silicon counterparts. However, ensuring these advantages are maintained for ...
GitHub

Logic Gates using LTspice

This repository explains the implementation of Logic Gates in CMOS Logic using LTspice Simulator. This shows the schematics of Logic Gates and plot the output waveform to verify the functionality.
GitHub

Sj1928/cmos-basics-LTSPICE-VLSI

Basic CMOS Circuits Simulated with LTspice This repository contains simulations of basic CMOS (Complementary Metal-Oxide-Semiconductor) logic circuits using LTspice. It includes the implementation of ...
EDN

CMOS-Based Logic Probe Circuit

The circuit was designed to create a handy logic probe that can show off the logic states for high, low and pulsing outputs with the use of CMOS 4001 integrated circuit. Logic Probe – a handheld probe ...